Микросхема SN74HC240DW, АП3

Характеристики

SN74HC240DW, АП3The SN74HC240DW is an octal Buffer/Line Driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. The HC240 device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

• High-current outputs drive up to 15 LSTTL loads
• 3-state Outputs drive bus lines or buffer memory address registers
• 80µA maximum ICC low power consumption
• 9ns typical Propagation delay (tpd)
• ±6mA Output drive at 5V
• 1µA maximum Low input current
• Green product and no Sb/Br

Микросхемы / Логические микросхемы / Микросхемы ТТЛ (серия 74)
Корпус: 20-SOIC, инфо: Логический элемент ТТЛ Шинный формирователь инвертирующий 2 х 4 бит КМОП кристалл, примечание: АП3