3c10db85d262b094e6b7a0caef5af4af

Микросхема SN74ABT574ADW, ИР37

34,30 руб.

x 34,30 = 34,30
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Склад №110-12 дней34,30руб.31,90руб.30,87руб.30,18руб.28,13руб.27,44руб.26,75руб.24,70руб.
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Склад №25-7 дней62,08руб.56,94руб.55,91руб.54,54руб.50,76руб.49,74руб.48,36руб.43,56руб.
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Склад №35 дней80,26руб.74,09руб.72,37руб.70,66руб.65,86руб.64,14руб.62,77руб.56,25руб.
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Склад №47-10 дней41,16руб.37,73руб.37,04руб.36,02руб.33,61руб.32,93руб.31,90руб.28,81руб.
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Склад №55 дней79,23руб.73,06руб.71,34руб.69,63руб.67,57руб.65,17руб.61,74руб.55,57руб.

Характеристики

SN74ABT574ADW, ИР37The SN74ABT574ADW is an octal edge-triggered D-type Flip-flop with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

• Ioff Supports partial-power-down mode operation
• Latch-up performance exceeds 500mA per JEDEC Standard JESD 17
• Green product and no Sb/Br

Микросхемы / Логические микросхемы / Микросхемы ТТЛ (серия 74)
Корпус: 20-SOIC (0.295», 7.50mm Width), инфо: Логический элемент ТТЛ триггер D-типа с тремя состояниями на выходе, примечание: ИР37