4ed2e5a22dea779688f9fc9e5a45d5c0

Микросхема CD74HC390E, ИЕ20

50,96 руб.

x 50,96 = 50,96
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Склад №110-12 дней50,96руб.47,39руб.45,86руб.44,84руб.41,79руб.40,77руб.39,75руб.36,69руб.
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Склад №25-7 дней92,24руб.84,59руб.83,06руб.81,03руб.75,42руб.73,89руб.71,85руб.64,72руб.
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Склад №35 дней119,25руб.110,07руб.107,53руб.104,98руб.97,84руб.95,30руб.93,26руб.83,57руб.
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Склад №47-10 дней61,15руб.56,06руб.55,04руб.53,51руб.49,94руб.48,92руб.47,39руб.42,81руб.
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Склад №55 дней117,72руб.108,54руб.106,00руб.103,45руб.100,39руб.96,82руб.91,73руб.82,56руб.

Характеристики

CD74HC390E, ИЕ20The CD74HC390E is a high speed CMOS dual decade Ripple Counter pin compatible with low-power Schottky TTL (LSTTL). It is divided into four separately clocked sections. The counter has two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the high-to-low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section.

• Two master reset inputs to clear each decade counter individually
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• High noise immunity
• Direct LSTTL input logic compatibility
• CMOS Input compatibility

Микросхемы / Логические микросхемы / Микросхемы ТТЛ (серия 74)
Корпус: 16-PDIP, инфо: Логический элемент ТТЛ счетчик десятичный 4 бита КМОП кристалл, примечание: ИЕ20