a69bb459b08ffcd751022ce0110af773

Микросхема CD4042BE, Триггер D-типа х 4 (=КР1561ТМ3) [PDIP-16]

17,64 руб.

x 17,64 = 17,64
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Склад №110-12 дней17,64руб.16,41руб.15,88руб.15,52руб.14,46руб.14,11руб.13,76руб.12,70руб.
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Склад №25-7 дней31,93руб.29,28руб.28,75руб.28,05руб.26,11руб.25,58руб.24,87руб.22,40руб.
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Склад №35 дней41,28руб.38,10руб.37,22руб.36,34руб.33,87руб.32,99руб.32,28руб.28,93руб.
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Склад №47-10 дней21,17руб.19,40руб.19,05руб.18,52руб.17,29руб.16,93руб.16,41руб.14,82руб.
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Склад №55 дней40,75руб.37,57руб.36,69руб.35,81руб.34,75руб.33,52руб.31,75руб.28,58руб.

Характеристики

CD4042BE, Триггер D-типа х 4 (=КР1561ТМ3) [PDIP-16]The CD4042BE is a CMOS Quad-clocked ‘D’ Latch, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY=0 the transfer occurs during the 0 CLOCK level and for POLARITY=1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY=0 and negative for POLARITY=1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.

• Clock polarity control
• Q and Q outputs
• Common clock
• Low power TTL compatible
• Standardized, symmetrical output characteristics
• 100% Tested for quiescent current at 20V